All digital Class-D modulator and its saturation protection techniques

ABSTRACT

Methods and systems for modulating an input electrical signal are disclosed and may comprise modulating input signals utilizing a digital Class-D modulator and generating a digital output signal that is proportional to the input signals. The digital Class-D modulator may be comprised of four stages. To avoid integrator saturation, the output of at least one integrator stage may be limited by utilizing limiters in integrator feedback loops. The digital Class-D modulator utilizes a pulse width modulation technique. For increased signal to noise ratio (SNR) at a desired output power, the magnitude of a triangular waveform oscillator voltage may be greater than the magnitude of an integrated input signal. The digital output signal may be fed back to an input of at least one of the four stages in the digital Class-D modulator. The triangular waveform oscillator frequency may be adjusted to match desired output frequency.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

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FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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FIELD OF THE INVENTION

Certain embodiments of the invention relate to electrical signalmodulation. More specifically, certain embodiments of the inventionrelate to a method and system for an all-digital class-D modulator andits saturation protection techniques.

BACKGROUND OF THE INVENTION

Mobile phone technology is continually being improved to increaseefficiency and reduce handset size, weight, and battery requirements.Reduced power consumption leads to smaller, lighter handsets with longertalk times. Increased efficiency is necessary for increased batterylifetime, as well as to support the ever-increasing features designedinto mobile phones. Features such as MP3 players, FM radio, videoplayers, and even televisions are being integrated into portablehandsets. A common aspect of all these features is audio, thus requiringhigh quality audio amplification with minimal power usage. In additionto the RF amplifier circuit, one of the main power usage components inmobile phone handsets is the audio amplifier circuitry.

The audio output requirements of a mobile phone handset include apowerful polyphonic ring tone, natural and clear voice reproduction, andclean, noise-free music reproduction, either through headphones orearphones, or over the hand set built-in speaker. Thus, the system maybe capable of delivering high output power for built-in speakeroperation, lower power but high quality audio output for voice or musicplayback, and low power consumption when idle. Even when no input signalis present, such as in a lull in conversation, there is stillsignificant power usage by the audio circuits. One technique to reducepower usage is to shut down audio amplifiers when no input signal ispresent. Another is to improve the efficiency of the amplifier.

Primary factors in audio amplifier performance include frequencyresponse, gain, noise, and distortion. While it is highly advantageousto increase battery lifetime, it must be accomplished withoutsacrificing audio signal output quality, i.e. maintaining high gainwhile suppressing noise and distortion.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for an all-digital Class-D modulator and itssaturation protection techniques, substantially as shown in and/ordescribed in connection with at least one of the figures, as set forthmore completely in the claims.

Various advantages, aspects and novel features of the present invention,as well as details of an illustrated embodiment thereof, will be morefully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary digital Class-D digitalmodulator in accordance with an embodiment of the invention.

FIG. 2 is a diagram illustrating an exemplary digital Class-D digitalmodulator signal transfer function (STF) and noise transfer function(NTF) frequency response in accordance with an embodiment of theinvention.

FIG. 3 is a diagram illustrating an exemplary digital Class-D digitalmodulator output spectrum with input amplitude of 0.5 in accordance withan embodiment of the invention.

FIG. 4 is a diagram illustrating an exemplary modulator signal to noiseratio (SNR) versus output power in accordance with an embodiment of theinvention.

FIG. 5 is a block diagram of an exemplary digital Class-D digitalmodulator with feedback limiters in accordance with an embodiment of theinvention.

FIG. 6 is a diagram illustrating an exemplary digital Class-D modulatorwith feedback limiters signal to noise ratio (SNR) versus output powerin accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system formodulating an input electrical signal. Aspects of the method maycomprise modulating input signals utilizing a digital Class-D modulatorand generating a digital output signal that is proportional to theanalog input signals. The digital Class-D modulator may comprise fourstages. To avoid integrator saturation, the output of at least oneintegrator stage may be limited by utilizing limiters in integratorfeedback loops. The digital Class-D modulator utilizes a pulse widthmodulation technique. For increased signal to noise ratio (SNR) at adesired output power, the magnitude of a triangular waveform oscillatorvoltage may be greater than the magnitude of an integrated input signal.The digital output signal may be fed back to an input of at least one ofthe four stages in the digital Class-D modulator. The triangularwaveform oscillator frequency may be adjusted to match desired outputfrequency. The gain stages in the digital Class-D modulator may beprogrammed to tune the signal transfer function (STF) and noise transferfunction (NTF).

FIG. 1 is a block diagram of an exemplary digital Class-D digitalmodulator in accordance with an embodiment of the invention. Referringto FIG. 1, the exemplary digital Class-D modulator may comprise fourstages 141, 143, 145, and 147 with adders 103, 109, 117, and 123,integrators 105, 111, 119, and 125, integrator gain stages 107, 115,121, and 129, and resonator gain feedback loops 113 and 127. In additionto the four stages, the exemplary digital Class-D modulator may comprisea triangle waveform generator 131 and a comparator 137.

The input signal X(n) 101 may be applied at the positive input to theadder 103. The output signal Y(n) 139 feedback loop and the resonatorgain feedback loop 113 may be communicated to the negative inputs ofadder 103. The output of adder 103 may be coupled to the input of theintegrator 105 which may then be coupled to the integrator gain stage107. The output of integrator gain stage 107 may be coupled to thepositive input of adder 109 along with the output signal 139communicated to the negative input of adder 109. The output of the adder109 may be communicated to the integrator 111, the output of which maythen be communicated to the integrator gain stage 115. The output of theintegrator gain stage 115 may be coupled to a negative terminal of adder103 through the resonator feedback loop 113 and also to the positiveinput of adder 117.

In addition, the resonator feedback loop 127 and the output signal Y(n)139 may be communicated to the negative inputs of the adder 117. Theoutput of the adder 117 may be coupled to the integrator 119, the outputof which may then be coupled to the integrator gain stage 121. Theoutput of the integrator gain stage may be coupled to the positive inputto adder 123. In addition, output signal Y(n) may be communicated to thenegative input of adder 123. The output of the adder 123 may be coupledto the integrator 125, the output of which may be coupled to theintegrator gain stage 129. The output of the integrator gain stage 129,Vint 135, may be communicated to an input terminal of the comparator137. This signal may also be fed back to a negative input of the adder117 through the resonator feedback loop 127. The output of thetriangular waveform generator 131 may be coupled to another input of thecomparator 137. The output Y(n) 139 of the exemplary digital Class-Dmodulator may be defined as the output of comparator 137, which may alsobe fed back to a negative input of the adder 103 as well as to adders109,117, and 123.

In operation, an input signal X(n) 101 may be applied to the exemplarydigital Class-D modulator at the positive input to adder 103. The outputsignal Y(n) 139 and the signal from feedback loop 113 may be subtractedfrom the input signal X(n) 101 and may then be integrated and amplifiedby integrator 105 and integrator gain stage 107, respectively. Theoutput signal of the integrator gain stage 107 may be communicated tothe positive input to adder 109. The output signal Y(n) 139 may besubtracted from the integrated output from output gain stage 107 at theadder 109, and then integrated and amplified by the integrator 111 andthe integrator gain stage 115. The output signal from the integratorgain stage 115 may be fed back through resonator feedback loop 113 to anegative input to adder 103, and also communicated to a positive inputof the adder 117. The output signal Y(n) 139 and the signal from theresonator feedback loop 127 may be subtracted from the positive input toadder 117. The output signal from the adder 117 may be communicated tothe integrator and integrator gain blocks 119 and 121, and the output ofintegrator gain block 121 may be communicated to the positive input ofadder 123. The output signal Y(n) 139 may be subtracted from the signalat the positive input to adder 123, and the result may be applied to theintegrator and integrator gain blocks 125 and 129. The output signal ofintegrator gain block 129 may be communicated to one input of thecomparator 137, and also may be fed back to a negative input of adder117 through resonator feedback loop 127. The output of the triangularwaveform generator 131 may also be communicated to an input of thecomparator 137. In instances when the input signal Vint 135 may be lowerin magnitude than the input signal V_(osc) 133, the output of thecomparator 137 may be low, and when the input signal V_(int) 135 may behigher than the input signal V_(osc) 133, the output of comparator 137may be high. This may lead to pulse width modulation, where the width ofthe pulse may be proportional to the magnitude of the input signal Vint135.

The signal transfer function (STF) may be defined as the output signalY(n) 139 divided by the input signal X(n) 101. Applying this relation tothe above described circuit may result in the following equation:

$\frac{X}{Y} = \frac{c_{4}c_{3}c_{2}c_{1}z^{- 4}}{\begin{matrix}\lbrack {( {1 - z^{- 1}} )^{2} + {c_{2}c_{1}g_{1}z^{- 2}}} \rbrack \\{\lbrack {( {1 - z^{- 1}} )^{2} + {c_{4}{z^{- 1}( {1 - z^{- 1}} )}} + {( {1 + g_{2}} )c_{4}c_{3}z^{- 2}}} \rbrack +} \\{{c_{4}c_{3}{c_{2}( {1 - z^{- 1}} )}z^{- 3}} + {c_{4}c_{3}c_{2}c_{1}z^{- 4}}}\end{matrix}}$

Similarly, the noise transfer function (NTF) may be determined from theoutput signal Y(n) divided by a quantization noise of the circuit:

$\frac{Y}{N} = \frac{( {1 - z^{- 1}} )^{2}\lbrack {{c_{2}c_{1}g_{1}z^{- 2}} + ( {1 - z^{- 1}} )^{2}} \rbrack}{\begin{matrix}\lbrack {( {1 - z^{- 1}} )^{2} + {c_{2}c_{1}g_{1}z^{- 2}}} \rbrack \\{\lbrack {( {1 - z^{- 1}} )^{2} + {c_{4}{z^{- 1}( {1 - z^{- 1}} )}} + {( {1 + g_{2}} )c_{4}c_{3}z^{- 2}}} \rbrack +} \\{{c_{4}c_{3}{c_{2}( {1 - z^{- 1}} )}z^{- 3}} + {c_{4}c_{3}c_{2}c_{1}z^{- 4}}}\end{matrix}}$The STF and NTF may be utilized to determine the frequency response ofthe exemplary digital Class-D digital modulator. This may beaccomplished by inserting values for integrator gain and resonatorfeedback loop gain into the above equations.

FIG. 2 is a diagram illustrating an exemplary digital Class-D digitalmodulator signal transfer function (STF) and noise transfer function(NTF) frequency response in accordance with an embodiment of theinvention. Referring to FIG. 2, the exemplary digital Class-D digitalmodulator STF 201 and NTF 203 are shown with variables determined asdescribed below. The x-axis comprises frequency and the y-axis comprisesthe STF 201 and NTF 203 magnitude in dB. The upper plot shows the STF201 and NTF 203 over a frequency range of 0-12 MHz, whereas the lowerplot shows the same STF 201 and NTF 203 but over a smaller frequencyrange (0-200 kHz). The frequency range from 0-20 kHz is of interest inaudio applications, for example.

For stability of an exemplary digital Class-D modulator 100, the slewrate (SR), or switching speed, of the integrator output V_(int) 135 maybe less than the slew rate of the triangle waveform V_(OSC) 133. The SRof a sine wave, V_(int)=A_(i) sin(2*π*f_(u)*t+φ), may beA_(i)*2*π*f_(u), where A_(i) may be the amplitude of the signal, f_(u)may be the bandwidth of the STF, and π=3.14159. The SR of a triangularwaveform may be 2*A_(tri)*f_(osc), where A_(tri) may be the magnitude ofthe triangular wave signal and f_(osc) is the frequency of thetriangular waveform generator 131. Thus, the relation may follow as:Ai*2*π*f _(u)<2*A _(tri) *f _(osc).In instances where the input signals V_(int) 135 and V_(OSC) 133 may bethe same full scale amplitude of 1, this relation may simplify to:f_(u)<f_(osc)/πThus, for stability, the bandwidth f_(u)of the STF may be smaller thanf_(osc)/π.

Referring back to FIG. 2, there is shown exemplary STF and NTF curvesutilizing exemplary values for the integrator gain coefficients, c₁ toc₄, and the resonator gain coefficients, g₁ and g₂. In the lower plot ofFIG. 2, which shows the STF 201 and NTF 203 over a frequency range from0-200 kHz, but concentrating on the range from 0-20 kHz, the STF remainsrelatively flat, around zero dB, throughout the range, but the NTFremains more than 80 dB lower.

FIG. 3 is a diagram illustrating an exemplary digital Class-D digitalmodulator output spectrum 301 with input amplitude of 0.5 in accordancewith an embodiment of the invention. Referring to FIG. 3, the y-axiscomprises the simulated output spectrum 301 magnitude in dB and thex-axis comprises frequency in Hz. The simulated spectrum shows a minimumnear 20 kHz, in agreement with the results shown in FIG. 2. Thefrequency of the input signal in the simulation may be 2 kHz, which maycoincide with the spike 303 in the magnitude near 2 kHz. The resultingsignal to noise ratio (SNR) may be 113 dB, demonstrating the ability ofthe digital Class-D modulator to generate an output signal with highSNR.

FIG. 4 is a diagram illustrating an exemplary modulator signal to noiseratio (SNR) versus output power in accordance with an embodiment of theinvention. Referring to FIG. 4, the y-axis comprises SNR 401 in dB andthe x-axis comprises output power in dB, where 0 dB may coincide with 30mW power. The plot demonstrates an increase of SNR 401 with output powerto a peak of greater than 110 dB, and a sudden drop in SNR 401 aboveapproximately −4 dB in output power. The reduction in SNR 401 at higheroutput power may be a result of integrator saturation, which may beaddressed utilizing the design shown in FIG. 5.

FIG. 5 is a block diagram of an exemplary digital Class-D digitalmodulator with feedback limiters in accordance with an embodiment of theinvention. Referring to FIG. 5, the exemplary digital Class-D modulatorwith integrator limiters may comprise four stages 551, 553, 555, and 557with adders 503, 505, 513, 515, 523, 525, 533, and 535, integrators 507,518, 529, and 541, integrator gain stages 511, 521, 531, and 543,integrator limiters 509, 519, 527, and 539, resonator feedback loops 517and 537, triangular waveform generator 545, and comparator 547.

The input signal X(n) 501 may be communicated to the positive input ofadder 503. The output signal Y(n) 549 and the signal from resonatorfeedback loop 517 may be subtracted from the input signal X(n) by adder503. This signal may then be coupled to the adder 505 where the outputof the limiter 509 may also be coupled. The output of the adder 505 maybe coupled to the integrator 507, the output of which may be fed back tothe adder 505 through the limiter 509 and also to the integrator gainstage 511. The output of integrator gain stage 511 may be coupled to thepositive input of adder 513. The output signal Y(n) 549 may becommunicated to the negative input of the adder 513. The output of theadder 513 may be coupled to an input of the adder 515. The output of thelimiter 519 may also be coupled to an input of the adder 515. The outputof the adder 515 may be coupled to the integrator 518. The output of theintegrator 518 may be coupled to the input of the limiter 519 and to thepositive input of the adder 523. The output signal Y(n) 549 and theoutput of the feedback loop 537 may be communicated to the negativeinputs of the adder 523.

The output of the adder 523 may be coupled to the adder 525. The outputof the limiter 527 may also be coupled to the adder 525. The output ofthe adder 525 may be coupled to the integrator 529, the output of whichmay be coupled to the input of the limiter 527 and to the input of theintegrator gain stage 531. The output of the integrator gain stage 531may be coupled to the positive input of the adder 533. The output signalY(n) 549 may be communicated to the negative input of the adder 533. Theoutput of the adder 533 may be coupled to an input of the adder 535. Theoutput of the limiter 539 may be coupled to another input of the adder535, and the output of the adder 535 may be coupled to the integrator541. The output of the integrator 541 may be coupled to the input of thelimiter 539 and to the input of the integrator gain stage 543. Theoutput of the integrator gain stage 543 may be coupled to an input ofthe comparator 547 and also fed back to a negative input of the adder523 through the resonator feedback loop 537. The triangle waveformgenerator 545 may be coupled to another input of the comparator 547. Theoutput of the comparator 547 may be the digital Class-D modulator outputand may be defined as the output signal Y(n) 549. The output signal Y(n)549 may be fed back to negative inputs of adders 503, 513, 523 and 533.

In an embodiment of the invention, the values of integrator gains c₁,c₂, c₃ and C₄ of the integrator gain stages 511, 521, 531 and 543 may beprogrammed to tune the signal transfer function (STF) and noise transferfunction (NTF) of the digital Class-D modulator. In addition, the gaing₁ and g₂ in the resonator feedback loops 517 and 537 may also beprogrammed to tune the STF and NTF.

In operation, an input signal X(n) 501 may be communicated to a positiveinput of the adder 503. The output signal of gain stage 517 and theoutput signal Y(n) 549 may be subtracted from X(n) 501 at the adder 503.The resulting output may be added to the output of the limiter 509 bythe adder 505. The output of the adder 505 may be integrated by theintegrator 507. The output of the integrator 507 may be fed back to theadder 505 through the limiter 509, which may protect the integrator fromsaturating by limiting the integrator 507 output values between −2 and2. The output of the integrator 507 may also be amplified by theintegrator gain stage 511 before being communicated to the positiveinput of the adder 513. The output signal Y(n) 549 may be subtractedfrom the output of the gain stage 511, and the result may be summed withthe output of the limiter 519 before being integrated by the integrator518. The output of the integrator 518 may be fed back through thelimiter 519, which may protect the integrator 518 from saturating bylimiting the integrator 518 output values between −2 and 2. The outputof the integrator 518 may also be amplified by the integrator gain stage521. The output of the integrator gain stage 521 may be fed back to anegative input of adder 503 through the resonator gain feedback loop 517and also to the positive input of the adder 523. The output signal ofthe resonator feedback loop 537 and the output signal Y(n) 549 may besubtracted from the output integrator gain stage 521 at the adder 523.The output of the adder 523 may be summed with the output of the limiter527 by the adder 525, and the output signal of the adder 525 may beintegrated by the integrator 529.

The output of the integrator 529 may be fed back to the adder 525through the limiter 527, which may protect the integrator 529 fromsaturating by limiting the integrator 529 output values between −1and 1. The output of the integrator 529 may also be amplified by theintegrator gain stage 531 before being coupled to the positive input ofthe adder 533. The output signal Y(n) 549 may be subtracted from theoutput signal of the integrator gain stage 531 by the adder 533, andthen added to the output signal of the limiter 539 at the adder 535before being integrated by the integrator 541. The output of theintegrator 541 may be fed back to the adder 535 by the limiter 539,which may protect the integrator 541 from saturating by limiting theintegrator 541 output valuesbetween −0.5 and 0.5. The output of theintegrator 541 may be amplified by the integrator gain stage 543 andthen coupled to an input of the comparator 547. The output of integratorgain stage 543 may also be fed back to a negative input of adder 523 byresonator feedback loop 537. The output of triangle waveform generator545 may be compared to the output of the integrator gain stage 543 bythe comparator 547. In instances where the output signal of theintegrator gain stage 543 may be higher than the triangle waveformgenerator signal, the comparator 547 output may be high, and ininstances when the output of the integrator gain stage 543 may be lowerthan the triangle waveform generator 545 signal, the comparator 547output may be low. This may lead to pulse width modulation, where thewidth of the pulse may be proportional to the magnitude of the inputsignal.

FIG. 6 is a diagram illustrating an exemplary digital Class-D modulatorwith feedback limiters signal to noise ratio (SNR) versus output powerin accordance with an embodiment of the invention. Referring to FIG. 6,the y-axis comprises the signal to noise ratio (SNR) of an exemplarydigital Class-D modulator with saturation protection, as described abovefor FIG. 5. The x-axis comprises output power of the digital Class-Dmodulator where 0 dB corresponds to 30 mW output power. The SNRincreases with the output power and decreases sharply at higher power,as in FIG. 2, but with saturation protection, the SNR at 0 dB issignificantly higher, more than 80 dB with oscillator voltageV_(OSC)=1.00 V. The SNR at 0 dB may be increased even further to morethan 100 dB by increasing the oscillator voltage V_(OSC) to 1.25 V.

In an embodiment of the invention, a method and system is described formodulating an input electrical 501 signal utilizing a digital Class-Dmodulator 500 and generating a digital output signal 549 that isproportional to the input signal 301. The digital Class-D modulator 500may be comprised of four stages 551, 553, 555 and 557. To avoidintegrator saturation, the output of at least one integrator stage 507,518, 529, and 541 may be limited by utilizing limiters 509, 519, 527 and539 in integrator feedback loops. The digital Class-D modulator 500utilizes a pulse width modulation technique. For increased signal tonoise ratio (SNR) 600 at a desired output power, the magnitude of atriangular waveform oscillator voltage 561 may be greater than themagnitude of an integrated input signal 559. The digital output signal549 may be fed back to an input of at least one of the four stages 551,553, 555, and 557 in the digital Class-D modulator 500. The triangularwaveform oscillator 545 frequency may be adjusted to match desiredoutput frequency. The values of gain c₁, c₂, c₃and c₄in the gain stages511, 521, 531 and 543 in the digital Class-D modulator 500 may beprogrammed to tune the signal transfer function (STF) 201 and noisetransfer function (NTF) 203.

Certain embodiments of the invention may comprise a machine-readablestorage having stored thereon, a computer program having at least onecode section for communicating information within a network, the atleast one code section being executable by a machine for causing themachine to perform one or more of the steps described herein.

Accordingly, aspects of the invention may be realized in hardware,software, firmware or a combination thereof. The invention may berealized in a centralized fashion in at least one computer system or ina distributed fashion where different elements are spread across severalinterconnected computer systems. Any kind of computer system or otherapparatus adapted for carrying out the methods described herein issuited. A typical combination of hardware, software and firmware may bea general-purpose computer system with a computer program that, whenbeing loaded and executed, controls the computer system such that itcarries out the methods described herein.

One embodiment of the present invention may be implemented as a boardlevel product, as a single chip, application specific integrated circuit(ASIC), or with varying levels integrated on a single chip with otherportions of the system as separate components. The degree of integrationof the system will primarily be determined by speed and costconsiderations. Because of the sophisticated nature of modernprocessors, it is possible to utilize a commercially availableprocessor, which may be implemented external to an ASIC implementationof the present system. Alternatively, if the processor is available asan ASIC core or logic block, then the commercially available processormay be implemented as part of an ASIC device with various functionsimplemented as firmware.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext may mean, for example, any expression, in any language, code ornotation, of a set of instructions intended to cause a system having aninformation processing capability to perform a particular functioneither directly or after either or both of the following: a) conversionto another language, code or notation; b) reproduction in a differentmaterial form. However, other meanings of computer program within theunderstanding of those skilled in the art are also contemplated by thepresent invention.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiments disclosed, but that the present inventionwill include all embodiments falling within the scope of the appendedclaims.

1. A method for modulating an input electrical signal, the methodcomprising: modulating input signals utilizing a digital Class-Dmodulator with saturation protection provided via a limiter in afeedback loop in each of a plurality of stages of said digital Class-Dmodulator, wherein each of said plurality of stages comprises a digitalintegrator, a digital limiter, and a digital gain stage; and generatingby said digital Class-D modulator, a digital output signal that isproportional to said input signals.
 2. The method according to claim 1,wherein said digital Class-D modulator comprises a fourth-order digitalClass-D modulator.
 3. The method according to claim 1, comprisinglimiting an output of at least one of a plurality of integrators in saiddigital Class-D modulator utilizing at least one integrator feedbackloop in said digital Class-D modulator for said saturation protection.4. The method according to claim 3, comprising limiting by a limiterwithin said at least one integrator feedback loop, an output of said atleast one of a plurality of integrators.
 5. The method according toclaim 1, comprising modulating said input signals by said digitalClass-D modulator utilizing pulse width modulation.
 6. The methodaccording to claim 1, comprising comparing a magnitude of a voltage of areference signal comprising a triangular waveform oscillator signal witha magnitude of a signal generated from said input signals.
 7. The methodaccording to claim 6, comprising adjusting a frequency of saidtriangular waveform oscillator signal.
 8. The method according to claim1, comprising feeding back said digital output signal of said digitalClass-D modulator to an input of at least one of a plurality of stagesin said digital Class-D modulator.
 9. The method according to claim 1,comprising programming a gain of at least one of a plurality of gainstages in said digital Class-D modulator.
 10. A system for modulating aninput electrical signal, the system comprising: one or more circuits formodulating input signals, said one or more circuits comprising a digitalClass-D modulator and a limiter, wherein said one or more circuits areoperable to provide saturation protection via said limiter in a feedbackloop in each of a plurality of stages of said digital Class-D modulator,wherein each of said plurality of stages comprises a digital integrator,a digital limiter, and a digital gain stage; and said one or morecircuits are operable to generate a digital output signal that isproportional to said input signals.
 11. The system according to claim10, wherein said digital Class-D modulator comprises a fourth orderdigital Class-D modulator.
 12. The system according to claim 10, whereinsaid one or more circuits comprise one or more integrator feedback loopsthat enable said saturation protection for at least one integrator insaid digital Class-D modulator.
 13. The system according to claim 12,wherein said one or more circuits comprise one or more limiters utilizedin said at least one of said plurality of integrator feedback loops. 14.The system according to claim 10, wherein said digital Class-D modulatorutilizes pulse width modulation.
 15. The system according to claim 10,wherein said one or more circuits are operable to compare a magnitude ofa voltage of a reference signal comprising a triangular waveformoscillator signal to a magnitude of a voltage of a signal generated fromsaid input signal.
 16. The system according to claim 15, wherein saidone or more circuits enables adjustment of a frequency of saidtriangular waveform oscillator signal.
 17. The system according to claim10, wherein said one or more circuits are operable to feed back saiddigital output signal to an input of at least one stage of saidplurality of said stages of said digital Class-D modulator.
 18. Thesystem according to claim 10, wherein said one or more circuits comprisea plurality of integrator gain stages, wherein said one or more circuitsenable programming of at least one of said plurality of integrator gainstages.